资源列表
UartRecv
- Uart串口接受Verilog程序，用于开发板串口接受功能测试-Uart serial accept Verilog program for development board serial accept functional test
PtDdcCic3
- CIC三级抽取滤波器源代码，包括modelsim的仿真代码，已经测试过稳定性-cic 3 cascade filter source code， including modelsim simulation code， and test
xapp423
- xilinx的xapp423，关于pace进行约束IO管脚的应用案例，艰难找到的-xilinx s app. about Creating Pin-Out Prior to Implementation with PACE, hard to find out
arb
- arbiter code for dual ported ram
cell_arch
- cell architecture for dual port ram
third
- codes for dual ported RAM
cell
- codes for DP ram synthesizable
csa_32
- The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used.-The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used.
DE2_70_VGA_pattern_gen
- 基于DE2-70的VGA彩条产生程序，适合初学者理解VGA的工作原理-VGA pattern generate in DE2-70
Introduction-to-verillog_good-document
- Introduction to verillog_good document
PWM
- System Verilog语言,功能为实现PWM波形-System Verilog
cube_root
- cube_root使用Verilog语言使用开立方根的算法-cube root