资源列表
chap7
- 小例子,关于Verilog HDL语言的一些小练习,可供初学者进行参考.
LAB1-TEXT
- LAB 1 - Basic Verilog
etyft
- 123 紧固件钢结构竟复活方法还库呼呼有客户部衣服和发叫一分耕耘给软硬件-sorry i you she he it vidieo
VHDL
- 本程序是些用VHDL应用的一些基本程序，有分频器，编译码器等一些基本器件程序-This program is using VHDL applications, some of the basic program, a divider, codecs, etc. some of the basic device program
krtlcd
- 基于FPGA的液晶显示驱动知识研究，可在quartus II环境下运行-FPGA-based knowledge of liquid crystal display driver can be run in quartus II environment
verilog--traffic-lights
- 基于verilog的交通灯程序，实现了定时的灯的转换-verilog procedures for traffic lights
chap7
- 《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4
Puncture
- OFDM编码技术中，删余模块的编码，包括了2/3和3/4-OFDM coding, the coding puncturing module, including 2/3 and 3/4
nor_flash_core
- Verilog实现的NOR FLASH控制器，基于M25P128开发，功能完整，简洁易懂，自用无问题。-Verilog implementations NOR FLASH controller, based M25P128 development, full-featured, easy to read, for personal use, no problem.
FPGAspwm
- 在Xilinx公司的Spartan ⅡE系列的XC2S100E pq-208 FPGA芯片上完成PWM波和SPWM波控制信号，控制电力电子器件IGBT和MOSFET构成的斩波、逆变输出电路，实现直流稳压和SPWM交流调频输出。-In Xilinx' s Spartan Ⅱ E Series XC2S100E pq-208 FPGA chip to complete SPWM wave PWM control signal wave and control the power electro
PCR
- 本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。-This procedure is in the transport stream during transmission of program the clock to carry out field testing and modification, using Verilog HDL language programming.
eetop.cn_emif_brg
- fpga与DSP通过emif接口通信，fpga内部通过fifo进行数据缓存-fpga with the DSP through emif interface communication, fpga internal data cache by fifo