资源列表
verilogwirereg
- 本文介绍了Verilog硬件描述语言中，wire变量与reg变量的区别，非常经典-This article describes the Verilog hardware descr iption language, wire the difference between the variable and the variable reg, very classic. . .
ADC0809VHDL
- VHDL语言编写的程序，实现控制ADC0809的工作 -VHDL prepared by the procedures, the control Connection between ADC 0809
Code1
- This is a code for wireless point-to-point communication using Altera FPGA and TI s CC2500 transceiver-This is a code for wireless point-to-point communication using Altera FPGA and TI s CC2500 transceiver
r22sdf_bf1
- Verilog Implementation of Butterfly 1 of R22SDF algorithm
Trafficlightcontrol
- VHDL code for traffic light control
frequency_division
- 三分频电路是硬件工程师招聘中必考题目，看似简单却能够挂到很多人，这里给出三分频的VHDL设计，其他奇数分频电路均可以参考此分频设计。其中并附有简单的偶数分频设计-Here are three points frequency VHDL design, other odd points frequency circuit can refer to this crossover design.
Coding
- 这是用VHDL语言编写的4位比较器，用了三种描述进行编写-This is the VHDL language with the 4-bit comparator, used to prepare three kinds of descr iptions
tv_csync_gen
- Generator of composite synchronisation TV signal on Altera DE2-35 board.
Altera_EPCS_Configuration_Device
- Protel99库Altera_EPCS_Configuration_Device-Protel99 Library Altera_EPCS_Configuration_Device
vhdl.rar
- 一个很好用的串口的VHDL实现。。quartus2编译通过,Serial port with a very good realization of VHDL. . quartus2 compiled through
UC1697V
- UC1697V-带MTP功能 LCD驱动8080 Mode -UC1697V 8080 Mode
Nexys4_Master_ucf
- DIGILENT NEXYS MASTER UCF