资源列表
DEC_counter
- 数码管计数器，VHDL语言实现，可以完成对输入时钟的计数显示，采用三位数码管显示-Digital counter, VHDL language, to complete the count of input clock display, digital display with three
flash016d_top
- 控制FLASH读写的控制器verilog代码-Control of the controller to read and write verilog code FLASH
fpga_dds
- 设计一个直接数字频率合成(DDS，Direct Digital Synthesis)，DDS是一种新型的频率合成技术。DDS 技术是一种把一系列数字形式的信号通过DAC 转换成模拟信号的合成技术。-Design a direct digital frequency synthesis (DDS, Direct Digital Synthesis), DDS is a kind of new type of frequency synthesis technologies. DDS technol
verilog_key_music
- 系统时钟50 MHZ 按键输入 蜂鸣器输出-The system clock is 50 MHz Press to enter Buzzer output
E2PROM-based-SPI-bus-protocol
- 基于串行E2PROM-S25C0x0A的SPI总线协议，中文版的-Serial E2PROM-S25C0x0A based on the SPI bus protocol, the Chinese version of
EEPROM
- VHDL语言写的IIC实现EEPROM，很好的程序，已经用过，没有问题-Written in VHDL language IIC achieve EEPROM, good procedures are used, there is no problem
dianzizhong
- (1) 设置复位功能 (2) 设置启/停功能 (3) 计时精度大于0.01s (4) 最长计时时间为24h （5）闹钟 （6）设定时间 （7）正点报时 -(1) set the reset function (2) set up Kai/stop function (3) is greater than the accuracy time 0.01s (4) the longest time to time 24h (5
DE2_70_CAMERA_V1.0.3
- terasic 5mp camera also quartus 9.1 support
Senior-Advanced-FPGA-design
- FPGA设计高级进阶，讲述了流水线，乒乓操作，异步时钟域处理，状态机等内容-Senior Advanced FPGA design, about the line, ping-pong operation, asynchronous clock domain processing, state machine, etc.
CPLD
- 数字频率计在FPGAEP4CE10F17C8上的功能实现和运用(Application of digital cymometer in FPGA)
BCD counter( state machine)
- a vhdl source code for BCD
Synopsys_Graphical_Environment_User_Guide
- Synopsis软件图形界面操作指南，对FPGA/ASIC初学者很有用！-Synopsis software GUI operation guide for the FPGA/ASIC is useful for beginners!