资源列表
FPGA_NiosII-
- 基于NiosII系统的百兆网卡控制程序,VHDL语言编写-Fast Ethernet system based NiosII control program, VHDL language
test_28
- 系统时钟选择时钟模块的1Hz时钟，黄灯闪烁时钟要求为1Hz，红灯15s，黄灯5s，绿灯15s(The system clock selects the clock of the clock module of the 1Hz, the yellow light scintillation clock is required for 1Hz, the red light 15s, the yellow light 5S, the green light 15s)
ALU-Design
- 8 bit alu design features: optimized design inclusive of multiplier
145103015
- Verilog source code for using keypad module with zybo fpga board to take input and show output to onboard leds and led module connected to GPIO
Experiment02
- FPGA黑金开发板实验教程，实验2的源代码。实验手册见《verilog那些事儿》-Black gold FPGA development board test tutorials, experiment 2 source code. Laboratory manual, see " verilog that thing"
11.23
- 电子音乐盒,实现do re mi的功能.-dianziyinyuehe
lcd12864
- 用LCD12864显示中文字符。采用verilog语言编写代码，LCD12864带字库。-LCD12864 display Chinese characters. Verilog languages code, LCD12864, with character.
OV9715
- OV9715的datasheet，用来实现对OV9715的时序控制-OV9715 the datasheet, OV9715 is used to achieve timing control
Ethernet
- Its the source code and complete documentation of 10G Ethernet.
AlteraFPGACycloneDemo6-BEEP
- Example shows how to program Altera FPGA Cyclone Family using VHDL Programming Language
noisII_2
- 这是基于FPGA的SOPC嵌入式系统的第二个实例。很不错-This is the FPGA-based SOPC second instance of embedded systems. Very good
DOC
- To switch relays using CPLD