资源列表
mb
- 简单秒表(1分钟)，希望对初学者有帮助，VHDL-Simple stopwatch (1 minute), want to be helpful for beginners, VHDL
VGA_VERTICAL
- vertical synchronization signal generation using verilog
11111
- 1、用FPGA/CPLD实现HS162字符液晶显示。 2、分析相应的功能要求，分析CPLD与字符液晶HS162的接口典型电路。 3、利用状态机的设计方法，通过指令编程实现对HS162-4液晶模块的读/写操作，以及屏幕和光标的操作。 4、编写模块的Verilog HDL语言的设计程序。 5、在Quartus II软件或其他EDA软件上完成设计和仿真。 -This design of a CPLD-based controls HS162 to achieve character
dds_dual
- Altera FPGA 双路DDS，频率相位可预制-Altera FPGA double DDS road, frequency phase can be prefabricated
mpfw_rev9
- 实用的程序代码，希望对大家有用，已经调试通过
multi
- multicycle bvbj vhdl-multicycle bvbj vhdl
LS_TX_RX
- 利用altera公司的FPGA使用verilog语言实现八位串口通信功能 -Altera FPGA using the verilog language to achieve the eight serial communication function
The_cpu_of_the_VHDL_language_programming
- 有关cpu的VHDL语言编程The cpu of the VHDL language programming不错的例子程序-The VHDL language programming the cpu The cpu of the VHDL language programming examples of good procedures
ispLEVER培训教程
- ispLEVER是LATTICE的CPLD、FPGA继承开发环境-ispLEVER CPLD, FPGA development environment succession
n2cpu_nii5v1
- This the Quartus Handbook-This is the Quartus Handbook
mux4to1-1
- vhdl co of the multiplexer 4 to 1
lab_instructions3
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is