资源列表
cic
- 在MATLAB2007A/SIMULINK环境下用DSP BUILDER8.0实现了五级CIC，解决了溢出问题。生成了可用的VHDL文件。- DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
weixingjisuanjijishu
- 微型计算机技术及描述里面介绍了D/A,A/D转换和有关计算机控制方法-computer
clock
- 用VHDL写的带有小时，分钟，秒的电子钟，已在FPGA开发板上调试运行过，显示very well!-Written in VHDL, with the hours, minutes, seconds, the electronic clock has been running in the FPGA development board debugger before, show very well!
MUSIC
- 16*16点阵循环显示8个汉字，有背景MIDI音乐输出，有一个键盘控制音乐的选择，还附带乐曲弹奏功能。有比较详细的注解。-16* 16 dot matrix display cycle of 8 Chinese characters, with background MIDI music output, there is a keyboard to control the choice of music, but also with music playing capabilities. Mor
counter10
- 这是一个十进制的计数器哦，是用vhdl语言开发出来的 是一个不错的十进制计数器-This is a decimal counter Oh, is vhdl language developed is a good decimal counter
reg4b
- 这是一个4位的锁存器 一般适用于4位十进制计数器上-This is a 4-bit latch generally apply to 4-bit decimal counter
r2000project_pipeline
- verilog mips pipelie perpect
vhd2vl2
- transrator verilog to vhdl
diglab3
- lcd test on the altera de2 board with switches and leds
xq_Test7
- VHDL语言编写一个BCD计数器并在七段显示数码管上显示的程序,实现了动态扫描，而且很好用-VHDL language a BCD counter and in the seven-segment display digital tube display process to achieve a dynamic scanning, and it just works
COUNT60M
- 六十进制计数器，带进位输出，很简单，基本实现啦所要求的功能-6 decimal counter, into the digital output, is very simple, basic functionality required to achieve啦
choic6-1
- 实现六选一的功能，六位四进制输入，实现同步位选，再加一个译码器就可以实现动态扫描和译码了-Achieve the six elected a function of 6 4 binary inputs, synchronization Choice, coupled with a decoder can be dynamically scan and decode the