资源列表
PWM
- 使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。-The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..
finalvhdl
- 这个一个密码锁的程序，在蓝宝石开发板上跑的。预先设置四位密码，如果输入对了就显示正确，如果输入错误连续三次就锁住。-A lock of this program, the development board running sapphire. Four pre-set password, if the input is displayed on the right, if you enter the wrong three times in a row lock.
frequency-demultiplier
- 电子分频器：有源电路，位于功率放大器之前，将前置音频信号分频后再用各自独立的功率放大器，把每一个音频频段信号给予放大，然后分别送到相应的扬声器单元-Electronic frequency divider: active circuits, in front of the power amplifier, will lead audio signal frequency and then separate the power amplifier, the every audio frequenc
iic_100k
- 用verilog HDL语言描述的i2C总线程序-a iic_100k program using a verilog HDL
TimeQuest-diary
- 关于TimeQuest的时序分析日志，属于时序分析的基础部分，对学习时序分析有很大帮助-a learning diary about TimeQuest analyse
fifo_pipeline_booth_multiplier
- fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器，并且使用了流水线描述方式，本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
pipeline_lut_multiplier
- pipeline_lut_multiplier, 一个使用查找表实现的流水线乘法器，本程序使用verilog HDL language 语言编写-pipeline_lut_multiplier ，a multiplier based on look up tablets ,and it is programing in verilog language
pipeline_streamlined_divider
- pipeline_streamlined_divider, 一个流水线的除法器，使用Verilog HDL语言编写-pipeline_streamlined_divider， a divider using pipeline technology in verilog HDL language
fifo
- FIFO FSM Implementation
RS_232_Test
- this file is a driver for rs-232 protocol. tx and rx. working for as uart protocol
sorter_block
- this is a code for a sorter block. read data a RAM and sort them. then write data in RAM-this is a code for a sorter block. read data a RAM and sort them. then write data in RAM
ALU
- Arithmetic and Logic Unit