资源列表
ti_C6474evm_fpga_top
- Project file for VHDL design
cach
- LEON2中cach部分VHDL代码 需要完整的请联系我-LEON2 VHDL code
verilog-code-style-specification
- 企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。-Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.
Verilog-HDL-Coding
- Motorala推荐的Verilog代码规范。对于VerilogHDL语言编写很有借鉴意义。-Motorala recommended Verilog code specifications. VerilogHDL language is useful for reference.
Tetris_final
- FPGA俄罗斯方块。 -采用VHDL编写，该游戏支持PS2键盘输入，VGA视频输出，游戏可以选择不同难度，同时可以记录显示游戏得分。-FPGA Tetris. - Use of VHDL, the game supports PS2 keyboard input, VGA video output, the game can choose different difficulty, while records show game scores.
verilog-experience-for-beginners
- VerilogHDL语言的设计经验，适合初学者入门学习，包含了Verilog编写时需要注意的很多方面，很有参考价值。-VerilogHDL language of design experience, suitable for beginners to learn, including the need to pay attention when writing Verilog many aspects of great reference value.
100-FPGA-question_Introduction
- FPGA经典100问之《入门与提高5问》。介绍了FPGA入门时的许多注意事项，对FPGA的快速入门很有帮助，初学者必备！-FPGA 100 and asked the classic " entry and improve 5 ask." It introduces many considerations when FPGA starter on quickstart helpful FPGA, beginner necessary!
100-FPGA-questions-Download
- FPGA经典100问之＜下载验证16问＞。介绍了FPGA在下载验证过程中的常见问题，对FPGA常见配置电路进行了讲解。-FPGA asked the classic 100 < Download verified 16 Q> . FAQ introduced FPGA verification process the download of FPGA configuration circuit common were explained.
32mto1m
- 主要实现将32Mhz的时钟，通过一个触发信号将其分成1Mhz的互补信号，总共十个周期的，十个周期后输出为零-The main achievement of the clock 32Mhz by a trigger signal will be divided into complementary signals 1Mhz, for a total of ten cycles, after ten cycles output is zero
sport
- 基于FPGA的数字秒表，通过按键开始计时，再次按下暂停，按下复位键清零-FPGA-based digital stopwatch, through the button to start timing, press pause again, press the reset button clears
clkdiv
- 对于fpga的时钟分频，编程方法，简单易懂，赠给各位学习fpga的同志们-For fpga clock frequency division, programming method, and easy to understand, to your learning fpga comrades
uart
- UART developement in VHDL