资源列表
m_xulie
- 这是用verilogHDL写的m序列发生器，简单易用，代码非常易读-It is written verilogHDL m sequence generator, easy to use, the code is very easy to read
AD_TLC549
- 这是用verilogHDL写的AD549的FPGA驱动代码，适用于通常的串行AD芯片-It is written in AD549 verilogHDL the FPGA driver code, applicable to the general serial AD chip
DA_TLC5620
- 这是用verilog写的基于FPGA的TLC5620串行DA的驱动代码，稍加修改后试用于通常的串行DA的驱动-This is a FPGA-based verilog write driver code TLC5620 serial DA, the latter slightly modified the trial in an ordinary serial DA driver
xor4b
- 四为异或门，实现全加器的硬件模块，使用VHDL语言实现，主要适用于初学者实例展示，为初学者提供quartus的实例展示。-4 bits xor gate finished with VHDL language， specifically for greenhands and bachelors who just begin with quartus
aaa
- 24位加法计数器，每一个信号的上升沿将使得计数器加1，实现从0 -1 -2 -3…… -22 - 23的循环计数器。-24 States adding type counter， every rising-edge signal increases the counter, and making sequence 0-1-2-...-22-23 cycled.
esjz
- 60-24 模拟时钟分钟小时计数器。 分钟为60标号的计数器从0-1-2-……58-59 循环往复，完成1个分循环，小时循环计数器加1；小时采用24小时制。-60-24 simulator of a clock, 60 is for minutes, starts 0 increased by 1,and cycle period is 60 once a cycle is finished, the 24 adding-type counter will increase by1 and
CPLD_PCIE20140613
- 本CPLD程序是针对PLX8311的PCIE局部总线状态机程序，可以实现基于PCIE X1的数据通讯，在实际项目中应用通过-The CPLD Program for PLX8311 the PCIE local bus state program, can be achieved based PCIE X1 data communication, in the actual project application by
led_shift
- 在xilinx的ISE上写的LED灯移动的verilog程序-a verilog code for led-shifting which writed with ise 14.2
Verilog-language-in-ASIC-design
- Inout bidirectional port programming based on Verilog language in ASIC design
E_watch
- 一款电子表芯片，能够能够显示年月日，星期，并且实现闰年的自动调整。-An electronic table chip that can be able to display the date, day of week, and automatic adjustment for leap year.
BKM
- 设计一个11位巴克码序列峰值检测器，巴克码序列为11’b 11100010010。要求 能够检测巴克码序列峰值； 在存在1bits错误情况下，能够检测巴克码序列峰值。 写出测试仿真程序-Design of a 11 Barker code sequence peak detector, Barker code sequence 11 b 11100010010. Claim Barker code sequence can be detected peak 1bits in
count
- 能实现秒分频的计数器,调用元器件，用VHDL语言编写-To achieve second frequency division counter，Calls components, written in VHDL language