资源列表
VHDL_DS18B20
- DS18B20的VHDL语言控制方式。D S18B20的VHDL语言控制方式。-DS18B20 control of the VHDL language. DS18B20 control of the VHDL language. DS18B20 control of the VHDL language.
Spread_Frequency
- spearding freqeuncy project by vhdl code
32mem-rw
- c++编写的32位存储器读写程序,完成向6116填入数据并显示的功能-c prepared by the 32 memory reading and writing procedures to be completed 6116 and complete the data showed that the function
BCD
- 基于VHDL语言，实现二进制转换为BCD码。-Based on the VHDL language, to achieve a binary code is converted to BCD.
VHDL-Example-2
- fir filter vhdl code
uart
- 关于串口发送的verilog代码，实验中经常用到，已经用FIFO-it is about the uart transmit verilog code,very useful in experiment.
digitalinterfaceuart
- 文件说明了在fpga/cpld中怎样实现数据接口及其实例了urat-note of the document they simply / cpld How Data Interface and the examples of urat
gal_16v8
- 基于GAL16V8D的一个时钟整开逻辑代码.Verilog编写!
check
- 用Verilog实现的序列检测器，可以检测出任意规定序列-Verilog implementation using the sequence detector
Arinc429
- 一个简单的429协议实现的VHDL语言代码，具备基本的429数据字的收发功能，并且仿真通过，效果一般。-A simple 429 protocol to realize the VHDL language code, with basic data words of 429 transceiver functions, and through simulation, the effect of general.
Microsoft
- 基于VHDL的分频器设计，这是源码希望对大家有用。
multiply
- 由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。-Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.