资源列表
65filter
- 65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程-65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole alg
OOB_control
- 串行传输协议sata的物理层的控制模块的状态机-Serial transmission agreement of the physical layer control module sata the state machine.
firlvboqi
- fir滤波器设计，是MATLAB设计的vhdl转换-VHDL fir digital filter design, MATLAB-based design of the conversion
vga_rtl
- VGA显示FPGA verilog代码.分辨率可设置。-VGA display verilog code for FPGA.resolution can be set
FPGA_AT24C16
- FPGA控制E2ROM的程序，内部使用的是多频计数器完成，简单易用-FPGA control E2ROM program, which uses multi-frequency counter is complete, easy to use
mouse
- ps/2 mouse interface
fifo_pipeline_booth_multiplier
- fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器，并且使用了流水线描述方式，本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
4LED
- 基于VHDL语言，实现对4位数码管显示。-Based on the VHDL language, to realize four digital tube display.
54764716
- 乘法电路，vhdl写的。用于VHDL基础学习-multiply
SourceCode
- That s a bunch of ALU control code for MIPS pipelined in Verilog!
stepping-motor-and--Digital-clock
- 在FPGA上运行，控制步进电机和数字时钟的程序-Running on the FPGA to control the stepper motor and digital clock program