资源列表
cotas
- Costas环是用来解调双边带抑制载波信号的,也是二相或四相移相键控信号解调的专用环路-Costas loop is used to double sideband suppressed carrier signal demodulation, and also two-phase or four phase shift keying signal demodulation of the special loop
www
- 实现三位二进制数相乘,含有进位位，根据乘法的过程二得出-the design is aimed at three bit digital to multiply
fpgalock
- 子密码锁，是需要主人记住自己的开锁密码，开门时只需要将密码输入，就可以开门，所以密码锁的核心问题就是密码的比对问题。-Child lock, is the need to remember your master password unlock, open the door just to the password input, you can open the door, so lock the core issue is the password of the alignment.
VHDL-based-8-bit-multiplier
- 基于VHDL的8位乘法器运算程序，运用移位迭代法运算得出-VHDL-based 8-bit multiplier operation procedures, the use of shift operations derived iterative method
choose-1-from-4
- VHDL语言编写的4选一编码器，已通过仿真验证，并附有波形图-VHDL language 4 select an encoder, has been verified by simulation, together with the waveform. .
fir_filter
- 常系数的FIR滤波器VHDL设计文件，在MUX+plusII调试通过-regular FIR filter coefficients of VHDL design documents, the debugging through MUX plusII
fir-ip-vhdl
- altera quartus fir ip核 vhdl程序 含测试文件-altera quartus fir ip nuclear vhdl program including test files
uart_rar_testbench
- code VHDL uart mode -code VHDL uart mode code VHDL uart mode
bridge
- 5416开发板VHDL脱机程序，实现与5416的通信及脱机逻辑-5416 development board VHDL offline program
IicController
- IIC slave controller source code
digital--clock
- 在Quartus II 平台下用verilog语言写的多功能数字钟-In the Quartus II platform with verilog language written multifunction digital clock
i2c_rx8025
- lm3s读取r8025芯片的代码，RTC序列-Lm3s read r8025 chip code