资源列表
0917afifo_s
- 采用同步异步信号的方式，将两个CLK统一到同一个时钟下工作，用同步FIFO实现异步FIFO-Asynchronous signals using synchronous way, two a clock CLK to the same uniform to work, using synchronous FIFO Asynchronous FIFO
Example1
- fifo verilog hdl along with test bench its hardware
SPI_to_I2C
- SPI和I2C转换的verilogHDL程序-SPI and I2C conversion procedures verilogHDL
cl_rx
- cameralink总线接口代码，用于接收cameralink协议传输的图像数据。从芯片随路时钟域切换到系统时钟域。 做cameralink接口相关的图像采集系统可以参考。其中的ram是lattice工具生产的。-cameralink bus interface code for the image data receiving cameralink protocol transmission. Switching chip clock domains with the way the sys
hdl
- 一个VHDL的小文件，经过测试可以使用。-A VHDL small files, the test can use,,,,
NIOS_USBDEVICE
- FPGA QUARTUS USB总线通讯模块程序，常用模块。-FPGA QUARTUS USB bus module ,written by vhdl tools,a useful module.
spimaster
- -- Descr iption : This core implements a SPI master interface. -- Transfer size is 4, 8, 12 or 16 bits. -- The SPI clock is 0 when idle, sampled on -- the rising edge of the SPI clock. -- The SPI clock is derived from the bus clock input
CONTROL_DAC
- Seno Generator, for Altera DE2-70 This is a generator of seno signal and the output will be displayed in the VGA DAC of the board
Pipeline-3.zip
- Verilog codes for pipelined processor,Verilog codes for pipelined processor
Binary_search_algorithm
- fpga implementation of binary search algorithm using verilog code
UART_TX
- verilog写的串口发送程序，具有单字节发送和多字节发送功能，附带testbench，可自行验证-verilog write serial transmission program, sending a single byte and multi-byte transmit function, with testbench, can verify their own
CPI
- verilog实现的简易通用型CPI接口-verilog easy to achieve CPI general-purpose interface