资源列表
5
- 串并转换程序，由串行输出转换为4位的并行输出
washmachine
- 实现洗衣机控制电路,利用Verilog语言实现了洗衣机的五种不同工作状态，非常好的代码-the code of washmachine controlling circuit
control_wrr
- 用VHDL语言实现的以09449为桥接芯片的PCI接口，很高兴与大家共享。
rs1
- 用C语言实现RS的编码和译码，程序简单但是很实惠。-In C of RS encoding and decoding procedures are simple but very affordable.
Chapter-6
- 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
i2c_slave_model
- I2C从机控制信号，控制I2C，保证正常工作 -I2C slave control signal, control, I2C, and guaranteed to work
keyboardtest
- 键盘控制电路，以4*4键盘输入作为范例，进行了说明
AS_FIFO_DESIGN_Verilog
- 使用Verilog硬件描述语言完成了一个异步FIFO的设计，供相关硬件开发人员参考。-Verilog hardware descr iption language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
music
- verilog HDL编写的文件，实现音乐播放，FPGA为EP2C8Q208C8N，编译通过，详细内容参考代码。-verilog HDL documents prepared, the music player, FPGA to EP2C8Q208C8N, compile, details reference code.
3-8translater
- 3-8译码器的verilog hdl程序，实现3-8译码功能-3-8 decoder verilog hdl procedures to achieve decoding functions 3-8
FIFO
- Verilog HDL语言编写异步FIFO-Verilog HDL language, asynchronous FIFO
packer
- verilog data packer verilog data packer-verilog data packer verilog data packer verilog data packer