资源列表
shift_register.用Verilog实现的移位寄存器
- 用Verilog实现的移位寄存器,可以实现左移、右移等功能,Using Verilog implementation of the shift register, you can achieve the left, shifted to right and other functions
vb和西门子plc连接实例
- vb和西门子plc连接实例 可以跟西门子S7-200的PLC直接相连
module-display
- 数码管显示1234,通过调整开关决定数码管显示顺序为1234或4321.-Digital display 1234, by adjusting the switch determines the order of the digital display 1234 or 4321.
16位快速乘法器
- VHDL语言实现的16位快速乘法器-VHDL of 16 rapid Multiplier
减法计数器
- EDA常用计数函数VHDL程序设计,减法计数器:可预置数:-common counting function EDA VHDL programming, subtraction counter : Preset :
fpga_A
- vhdl code for card pci to fpga
cpu16
- 对于初学者比较好的另一种简单的16位 CPU 本人的心血结晶-Good alternative for beginners a simple 16-bit CPU' s own brainchild
ddr_sdram
- 对ddrsdram操作,用VHDL语言实现,read,write的接口电路控制-Erase operation to read and write on the ddrsdram
usb_device
- verilog 的USB 设备访问程序,已经验证-verilog for usb device
plj
- 频率计,用于测试频率对,被测信号频率进行测量-Frequency meter, used to test the frequency of measurement, the signal frequency
Temp1
- rubics cube solver verilog
iic_88091
- 实现88091驱动 带iic驱动 可以通过网管控制盘 通过IIC更新配置参数-Achieve 88,091 iic driver can drive belt through the network control panel update configuration parameters through the IIC
