资源列表
DDSpro
- DDS技术的设计代码，利用quartus II编写，供大家参考-DDS technology design code
LCD-controller---VHDL
- vhdl languge, i use the vhdl language for lcd controller with de2 board.
LCD-controller---Nghia
- different code for lcd controller using de2 board with vhdl lanuage
asic-va-vlsi
- document for asis and vlsi.
led_flow
- 跑马灯的VERILOG程序编程，实现了数码管的一次点亮-VERILOG programming Marquee achieve a digital one is lit
16qam
- vhdl实现16qam,有规范接口，解释清楚-implemention of 16 qam, have atlantic interfaces
VGA
- 彩条信号发生器，用于产生和输出彩条信号。FPGA用。-Color bar signal generator for generating and outputting color bar signal. FPGA use.
code-pour-decim-poly
- this code is for a decimation filter with polyphase structure , so the original filter is decomposed by 5 filters which is the decimation factor in that case and each of them is selected each Fs/5
multiply_8_VHDL
- 由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and
60_binary_counter_vhdl_quartus2
- 一个60进制的计数器的VHDL源代码，测试可行。-a VHDL code of 60 binary counter and it test feasible.
jiajian
- 利用Verilog语言编写的按键实现数码管显示数字的加减，通过三个按键分别实现加1和减1操作 以及复位操作，BASYS2开发板验证。-Verilog language use buttons to achieve digital display digital subtraction achieve plus one and minus one operation and reset operation, BASYS2 development board were verified by thr
motor2
- Verilog编程实现步进电机的单双八拍的四路脉冲信号。采用28BYJ-48步进电机（驱动ULN2003）验证可以实现其正反转。-Single and double eight four-shot pulse signal Verilog Programming stepper motor. Using 28BYJ-48 stepper motor (driver ULN2003) verification can achieve its inversion.