资源列表
traffic_tb
- verilog， 铁路道口异步交通灯设计的testbench.-testbench for an asynchronous circuit that is to control the gates and red flashing light at a railway level crossing,
jtd
- 实现十字路*通灯控制 以及数码管显示 4个交通灯 以上板验证-Crossroads traffic light control and digital display four traffic lights above board verification
AD7606URAT
- Verilog实现高速AD7606数据采样，8通道，采样频率可调，支持串口数据发送，亲测可用。-Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.
JK-flipflop_vhdl
- FOR LEARNING PURPOSE... VHDL CODE OF JK FLIPFLOP
ram_test
- NIOS实现RAM-test,新做好一块带SRAM的FPGA板子，学习NIOS，必定可以用到的测试SRAM的代码。-NIOS achieve RAM-test, a new well with SRAM FPGA board, the learning NIOS, must be used to test SRAM code.
decoder_1
- vhdl code for decoder
13_vga256
- Verilog code for display VGA coding for the DE2 Board of FPGA
microwave-oven
- 基于VHDL的微波炉控制。拥有全部模块，以及电路总图设计。-microwave oven
clockdiv_teste
- Clock division program write in Verilog with selected divider (32 bits)
dds(9854)_test(sin_cos)(EP1C6)
- 通过FPGA控制DDS(AD9854)输出120M一下的双路正交信号，实现在通信和控制领域的应用。-Controlled by FPGA DDS (AD9854) output 120 m the dual orthogonal signal, realize the application in the field of communication and control.
adder_26
- 加法器 IPcore调用，如何添加调用，应该是26位的-Adder IPcore call, how to add call, it should be 26-bit
demand-number
- 检测一个正弦波峰值个数，大于某个固定值时报警。-Detection of a sine wave peak number, greater than a fixed value alarm.