资源列表
shiyan2
- FPGA换流的实验程序，因为没有信号发生器，无法给出4路PWM信号，就自己产生了开关状态信号，给换流用的-In other experimental procedures FPGA flow, because there is no signal generator, can not give four PWM signal generated on their own switch state signal converter used to
SDRAM-verilog
- SDRAM控制器.用verilog实现SDRAM的读写操作。-sdram coll
coinwasher2
- 自动投币洗衣机的控制器设计，包含按键消抖，控制器模块，数码管显示，对电机的控制信号输出。投两颗币将实现洗半桶，投三颗币实现洗一桶-Automatic coin washing machine controller design, including key debounce, controller module, digital display, the motor control signal output. Throw two coins will achieve half a bucket
codeacq
- 实现扩频通信系统中的码同步。应用vhdl语言，可以运行-Spread spectrum communication system code synchronization. Application vhdl language, you can run
CRC
- CRC源程序代码，基于FPGA开发环境的源代码。-CRC source code, FPGA-based development environment source code.
final-2
- 数字信号系统设计，使用VHDL进行模拟信用卡的使用，存钱，取钱-Digital signal system design, simulation using VHDL use of credit cards, to save money. . .
hospital
- 数字系统设计，模拟医院场景，使用VHDL语言完成医院的相应功能-Digital system design, simulation hospital scenes, using VHDL language to complete the hospital' s corresponding function
tushuguan
- 数字系统设计，模拟图书馆场景，使用VHDL完成相应的图书馆的相应功能-Digital system design, simulation library scene, using VHDL complete the appropriate corresponding function library
vending-machine
- 自动售货机，5角1元输入，三种饮料输出，余额不足或售完会闪烁相关信息。-THis is a simulator of Vending Machine on Basys2 in verilog. 5jiao and 1yuan as input, 3 chioces for drinks. If all are sold out or more money is need, corresponding signals will flash on the LED screen.
simple-pipeLine-CPU
- 简单的流水线CPU实现，基于MIPS指令集。-Simple pipelined CPU implementation, based on the MIPS instruction set.
stepper-motor-control
- stepper motor control
t_sensor
- 数字温度计的Verilog实现，有时钟控制模块，显示模块，温度计控制模块。-digital temperature sensor