资源列表
fifo_vhdl
- FIFO的VHDL编程，其中包括FIFO的读，写，满帧，半满帧信号驱动-FIFO of the VHDL programming, including the FIFO' s read, write, full frame, half-full frame signal drive
fenpin
- 分频器 8分频器 50 已经测试 可以用 代码可更改-Divider divider 8 has 50 percent can be used to test the code can change
quartusII
- quartusII最新使用指南，帮你快速上手quartusII。-about quartusII
ncof
- quartus2环境中设计的高速任意波形发生器-highspeed waveform generator in quartus2
ad7823.vhd
- ad7823的VHDL驱动程序，测试在quartus9.0下编译通过-ad7823 driver of VHDL, the compiler under test through quartus9.0
DE-II-I2C
- 基于DE II实验平台，读取音频信号的I2C总线控制程序- based on the DE II experimental platform, the audio signal read I2C bus control procedures
NIO-II-function
- NIOS II常用函数详解详细讲解了NIOS II中各种函数的使用方法-NIOS II explain commonly used functions on the NIOS II in detail in the use of a variety of functions
DE2_SD_Card_Audio
- DE2_SD_Card_Audio是基于DE II的音频从SD卡读入的VHDL语言程序-DE II on the basis of DE2_SD_Card_Audio audio from the SD card is read into the VHDL Language Program
CPU
- 本人主要是介绍CPU和运算器级联的程序，采用的是VHDL语言-I was to introduce the CPU and the main computing device cascade process, using the VHDL language
22
- 使用VHDL实现16进制的计数器的算法程序-Use VHDL to achieve 16 of the counter-band algorithm procedure
fpga
- 是一些很好的FPGA设计实例，对初学者很好，我就是学这个入门的-Are some very good examples of FPGA design, good for beginners, I learn of this entry
DDRSDRAM
- DDR SDRAM的veilog hdl程序，经过验证 效果不错-DDR SDRAM' s veilog hdl procedures, good results verified