资源列表
BusMasteringPCIExpressInAnFPGA
- This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex pr
sw-fpga96x_crk
- 关于fpga的代码，可以参考的看看，也许有帮助-On fpga code, you can reference to see, might be helpful
FIR
- 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
Code_VHDL_180_cases
- VHDL_180_例常见代码,很适合于vhdl语言的初学者.-VHDL_180_ cases of common code, it is suitable for beginners vhdl language.
pci_mcst
- ---简化版，实现PCI总线控制--- 器件：ep1c6 开发工具：QuartusII 功能：简化PCI总线接口，占用资源少； 实现单路曼彻斯特码的收发。---- Starter Edition, to achieve control of PCI bus devices---: ep1c6 development tools: QuartusII functions: simplify PCI bus interface, occupy less resources the
vhdl
- ps2 vhdl 实现键盘输入 数码管显示ascii码-ps2 vhdl
mul_algo
- contains codes for various multiplication algorithms and their reports for analysis
vhdl
- 很好的课件，有需要的朋友可以下去看下。很多比较简单的说明-Very good software, there is a need of a friend can go facie
SRAM_controller
- 对于想编写sdram控制器的人来说，值得借鉴-Sdram controller would like to prepare for the people, to learn
HDB3encoder
- 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。-Digital baseband signal transmission i
document2007620132345
- Project Name : SOPC-based Voiceprint Identification System
DieuKhienLED
- Shift LED on Spartan 3E kit board.