资源列表
Altiumdesigner6
- 一个可以在Altium designer 6 中导入（图片）BitMapConvertVer130的小程序-One can import Altium designer 6 (picture) BitMapConvertVer130 a small program
4bitcomp
- I try 4-bit comparator here in VHDL
SR_Latch
- RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit i
crc_8
- 用vhdl编写的CRC校验代码，仿真以及下载在板上测试通过-Prepared by the CRC checksum vhdl code, simulation, and download the on-board test
SEG7_LUT_8_0
- DE2开发平台7段显示VHDL代码，自己针对vilorg翻译成VHDL代码-DE2 Development Platform 7 show the VHDL code for vilorg translated into their own VHDL code
phase-locked
- 主要是关于锁相环的环路滤波设计与计算，非常经典的-Mainly on the phase-locked loop filter design and calculation, very classic
FFT
- FFT高速傅立叶变换 VHDL完整源码 文档密码：www.armjishu.com 更多资料下载，欢迎登陆网站 www.armjishu.com
LCD
- 用VHDL实现LCD的驱动电路的设计的源码-VHDL to achieve with the design of LCD source drivers, who are interested can look at the
BH1415
- 数控调频发射器的设计 开关式的锁相环BH1415的调频参考C程序-BH1415 c language for bh1415
shizhong
- 时钟程序设计，为用vhdl语言设计编写的电子时钟显示分秒位-Clock programming, vhdl language designed for use in the preparation of accurate digital electronic clock display
cpld
- CPLD VHDL 数码管程序 流水灯程序 时钟程序 -CPLD VHDL program LED lights water clock procedures procedures CPLD VHDL program LED lights process water clock procedures
jpeg.tar
- vhdl source for jpeg beginner