资源列表
VHDL
- VHDL的4bit*4bit的有符号无符号的乘法除法实现-VHDL unsigned signed to achieve the multiplication division
FGPA-SRAM-Programe
- FPGA编程方法介绍，方便学习VHDL,公供大家参考-fpga programe medoth, study hardware vhdl language
Pseudo-Random_Bit_Sequence_Generator_by_FPGA
- A spatiotemporal chaotic map is digitized to develop a highly paralleled PRBS generator that accommodates to FPGA (Field Programmable Gate Array) implementation in present paper.
FPGA_NEW_APPROACH_TO_IMPLEMENT_CHAOTIC_GENERATOR.
- In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the freq
All_Digital_DC2DC_Converters_on_FPGA
- The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to imp
HDLcodingstyle
- verilog HDL 代码综合风格，非常适合初学者-verilog HDL code integrated style, very suitable for beginners
jpegVerilog
- FPGA实现jpeg Verilog源代码-FPGA realization of jpeg Verilog source code
PLL
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is
23-10111
- a simple serial to parallel converter using XILLINX and VHDL (the number of the project represents the binary code used by the converter e.g 23- 10111)
iamgod
- this a very nice vhdl program for making shit and stuff... plz write back if any trouble with it-this is a very nice vhdl program for making shit and stuff... plz write back if any trouble with it..