资源列表
ds18b20
- ds18b20的介绍及时序，以及对ds18b20进行温度读写的vhdl程序，在quartus环境下进行编译仿真-Introduction ds18b20 and timing, as well as read and write ds18b20 temperature vhdl procedure quartus compiled simulation environment
quanjiaqi
- 4 级流水方式的8 位全加器-Way flow of 4 full adder 8. . . . . .
s
- 自动售饮料机-Beverage vending machine. . . . . . . . . . . . . . . . . . .
CRC
- CRC 编码-CRC code. . . . . . . . . . . . . . . . .
10010
- verilog实现序列10010检测-verilog to achieve detection of sequence 10010
wodeshji
- 在FPGA上，实现了一个多功能数字抢答器，设置四个抢答按钮，及若干控制台按钮，有计分，抢答，重置，及时等功能-In the FPGA, the realization of a multi-functional digital Answer, and set up four Answer button, and a number of console button, there are points, Answer, replacement, and other functions in tim
cd4000x
- CD4000 双3输入端或非门+单非门 TI CD4001 四2输入端或非门 HIT/NSC/TI/GOL 双4输入端或非门 NSC CD4006 18位串入/串出移位寄存器 NSC CD4007 双互补对加反相器 NSC CD4008 4位超前进位全加器 NSC CD4009 六反相缓冲/变换器 NSC CD4010 六同相缓冲/变换器 NSC CD4011 四2输入端与非门 HIT/TI CD4012 双4输入端与非门
VHDL_Hardware_Language
- vhdl硬件描述语言，对于进行FPGA、CPLD开发的人来说比较有用。-vhdl hardware descr iption language is fundamental to the FPGA, CPLD development of more useful people.
UART
- Universal async Transmitter Receiver
pwm
- Pulse width modulation
I2C_Master
- I2C program (Inter IC bus)
clk_div
- Clock division document