资源列表
divideUnit
- a verilog programmed divide unit
f_cout
- 基于Quartus II的8位十六进制频率计的项目设计，包含了项目文件和VHDL源代码-Quartus II-based 8-bit hexadecimal frequency of project design, including project documents and VHDL source code
fdiv
- 基于Quartus II的数控分频器的项目设计，实现对时钟信号的任意进制分频，包含了项目文件和VHDL源代码-NC-based prescaler Quartus II project design, implementation of the clock signal of arbitrary frequency band, including the project files and VHDL source code
count10
- 基于Quartus II的十进制加法计数器的项目设计，包含了项目文件和VHDL源代码-Quartus II based on the decimal adder counter the project design, including project documents and VHDL source code
efcount
- 完整的等精度频率相位计，包含了项目文件、VHDL源代码、RTL电路图-Such as the complete phase of the frequency accuracy, including the project document, VHDL source code, RTL circuit
Revised_Verilog_code
- 简弘伦：Verilog HDL IC设计核心技术实例详解 源代码,更新版本-Honglun Jian, Revised Edition. Source coude of " Core Techniques of IC design"
miaobiao
- 是电子手表的程序，基本上和市面上的电子表显示方式一样，XX：XX的格式-Procedures for electronic watches, and the market is basically the same manner as the electronic table shows, XX: XX format
vhdlrule
- 详细介绍vhdl编程，花了好大力气找到，很有用，适合初学者-Vhdl programming details, it took great efforts to find, very useful for beginners
vhdl
- vhdl例子综合，花了好大力气找到，很有用，适合初学者-vhdl examples of integrated, spent great efforts to find a good, very useful for beginners
glVHDL
- 一个VHDL的小集合，把代码打开把其中的use work.butter_lib.all一句去掉就基本可以应用-A small collection of VHDL, the code open to the use work.butter_lib.all sentence can be applied to remove the basic
butterfly
- 另一种蝶形运算的代码，可用quartusII6.0运用-A butterfly operation of the code, the use of available quartusII6.0
VHDL
- 打开代码去掉其中的use work.butter_lib.all ，便基本可以应用-Open the code to remove the use work.butter_lib.all, it can be applied to the basic