资源列表
CPLD
- 复杂可编程逻辑器件的初步介绍，通过一系列的简单例子，帮助读者熟悉开发环境和开发语言。-CPLD initial introduction, through a series of simple examples to help beginners master the basic development process
CircuitDesignwithVHDL[1]
- 这主要是学习vhdl和fpga设计的一些资料-study for vhdl and fpga
pctr
- verilog high discr iptive language
fpga_13
- fpage design 3 by zip file
fpga_12
- fpga design 2 by zip file
VERILOG
- verilog基础知识与快速提高练习,包括verilog的语法知识，以及一些基本操作-verilog
de2.1
- 这是一个基于FPGA/SOPC设计的简单串口程序，是FPGA硬件和niosII软件编程的结合。对初学者有很大的借鉴意义。在Quartus6.1和niosII6.1环境下编译通过，并且下载到板子上运行成功-This is based on FPGA/SOPC design a simple serial program is FPGA hardware and software combination niosII. Great for beginners reference. In Quartu
dds
- DDS数字频率合成器，使用很方便，整个工程下载，vhdl语言-DDS digital frequency synthesizer, using the very convenient to download the whole project, vhdl language
fpga
- On a distributed algorithm based on FPGA pipelined FIR filter of the article.
c54x_verilog
- TI 的TMS320C54X的DSP的芯片软核verilog源代码，可以帮助初学者深入了解该系列DSP片内资源核结构，值得参考！-TMS320C54X of TI' s DSP chip soft-core verilog source code, can help beginners a better picture of the family of DSP-chip resources, nuclear structure, it is also useful!
LeiFPGALDPC
- this document is for the difference
SOPC_Builder
- SOPC架构建立实例，针对altera公司的DE2开发板，其他开发系统也可以用-based FPGA , SOPC construct experiment