资源列表
verilog_HDL_examples
- 本书介绍了大量verilog HDL程序设计的实例，对于verilog语言学习者和从事相关工作的工程师来说，都有一定的学习和参考价值。-The book introduced the verilog HDL programming a large number of examples, the verilog language learners and engineers engaged in related work both in terms of learning and a certai
can_verilog
- 基于verilog开发的 ｃａｎ 接口 ＩＰ 核已经调试通过附有说明-can ip
VHDLtraining
- VHDL语言入门教学，比较全。适合入门的人看。-VHDL training
calculator_vhdl
- Design PC calculator controlled by PC, using FPGA .PC and FPGA are connected by USB. -Design PC calculator controlled by PC, using FPGA .PC and FPGA are connected by USB.
vhdl_programs
- This the course for VHDL programming-This is the course for VHDL programming
Ctl_LCD
- 采用FPGA控制LCD。程序中用了两个状态机-FPGA to control the use of LCD. Procedures with two state machine
CPLD_CD
- 《CPLD开发实例》的配套光盘文件，包含大量的CPLD小程序，用VHDL语言描述-" CPLD development of examples of" CD-ROM of supporting documents, including a large number of small procedures CPLD, VHDL language used to describe
VHDL_VerilogHDL
- VHDL与Verilog语言的简明教程，介绍了用这两种语言进行硬件设计的基本方法与思路。-VHDL and Verilog language concise tutorial on using both hardware design language of the basic methods and ideas.
FPGA_Design_experience
- 讲解了在FPGA中时序设计时应该注意的问题，并分享了设计经验-On timing in the FPGA design should pay attention to the issue and to share the experience of the design
CPLD_CODE
- CPLD的小程序集合，VHDL语言描述，可直接用quartus打开-CPLD collection of small programs, VHDL language descr iption can be directly opened with quartus
vhdl
- 抢答器里的基本原程序,抢答模块，计时器电路JSQ的VHDL源程序，译码器电路YMQ的VHDL源程序-VHDL
verilog-Perl-3.120.tar
- Verilog Parser in Perl