资源列表
ol_no_corr
- OL NO CORRECTION VHDL SOURCE CODE
SA_VHDL-
- a simple serial adder in vhdl, enjoy it
conv_encoder
- TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码-Tail-biting convolutional code encoder verilog code
MSK
- FPGA中实现的MSK调制，带modelsim仿真。实际系统测试通过：载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页-MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation blo
DSB
- FPGA中实现的DSB的AM调制，带Modelsim仿真，实际测试通过：载波频率，信号频率以及调制度可调。-The FPGA implemented in the DSB AM modulation with Modelsim simulation, the actual test: the carrier frequency, and modulation signal frequency is adjustable.
FSK
- FPGA实现FSK调制，带Modelsim仿真，实际系统测试通过，载波信号，信号频率等可调。-FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.
BPSK
- FPGA实现BPSK调制，带Modelsim仿真，实际系统测试通过，载波信号，调制波信号频率可调-FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable
scr
- 12864显示字符和汉字 ，驱动12864,包括初始化/地址和数据的写 -12864 display characters and Chinese characters, the driver 12864, including the initialization/address and write data
ARM_37numbers_32bits
- ARM架构下的32位37个寄存器组的verilog源码-ARM architecture 32 37 register banks verilog source
MIPS_32numbers_32bits
- MIPS架构下的32位32个寄存器组的verilog源码-MIPS architecture 32 32 register banks verilog source
ARM_shift_32bits
- ARM架构下的32位桶形移位器的verilog源码-32-bit barrel shifter verilog ARM architecture of the source
MIPS_shift_8bits
- ARM架构下的8位桶形移位器的verilog源码-8 barrel shifter ARM architecture of verilog source