资源列表
06121923
- Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
simple_ram
- the file about simple ram by VHDL code
06135529
- A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
06208897
- Reduced-Complexity LCCReed–Solomon Decoder Based on Unified Syndrome Computation
nios2ex1
- 很好的一个verilog 历程,适合初学者,很有帮助-a good case
VHDL
- vhdl adder full adder for basic tutorial
10022696KAI_HE
- RISC 处理器 实现 d=a or b and c-RISC PROCESSOR d=a or b and c
08_uart
- fpga 串口程序，实现串口接收并自动发送-FPGA serial procedures, serial receiving and automatic transmission
Decimal-module
- 这是秒表设计的一部分，十进制是秒表设计中比较常用的方法-This is part of a stopwatch designed decimal stopwatch design is more commonly used method
LCDDriver
- Displaying an image from the OV7679 camera to the RGB 4.3inch display without the use of RAM. The method of switching the clock signal in CPLD
ALTmax2_HC_SR04
- Measurement HC-SR04 and output to dynamic led display (Altera MAX2)
SDRAM
- 这篇文档主要是介绍了SDRAM的相关原理，以及时序的一些描述，是学习SDRAM的一篇不错的文档-This document mainly describes the relevant principles SDRAM, as well as the timing of some descr iption, is to learn a good documentation of SDRAM