资源列表
cf_fft
- 用verilogHDL写的实现4096点FFT的算法，附带quartus ii工程.-VerilogHDL achieved with 4096-point FFT written algorithm works with quartus ii
UART
- URAT设计，系统包括五个模块，MCU模块，TX发送模块，RX接受模块，波特率产生模块，复位模块。-URAT design, the system consists of five modules, MCU module, TX transmit module, RX accept modules, baud rate generator module, reset module.
altera_cordic-Verilog
- altera_cordic sin cos altera_cordic sin cos-altera_cordic sin cos
frm_sync
- 此程序为帧同步程序，采用状态机的VHDL描述方式编写。-This procedure for frame synchronization procedures, using the state machine to prepare the way VHDL descr iption.
sign_det
- 此程序为符号检测的VHDL程序，用于检测输入数据的最高位符号。-This program is a symbol detection VHDL program for detecting the most significant bit of input data symbols.
jpegencode
- Verilog源码，实现jpeg图片的编解码,内附代码说明文档。-verilog source code to realize the encodeing and decodeing for JPEG
mux16
- 16*16位的乘法器 ， 包含仿真文件-16* 16-bit multiplier, including simulation files! ! ! ! ! ! ! ! ! !
ADPUARTPDPRAM
- ad7606采集信号数据存入双口ram再通过串口发送出去。- ad7606 collected signal data stored in the dual port ram and then sent through the serial port.
AD7606PFSM
- AD7606利用状态机进行模拟时序控制采样。-AD7606 using the state machine to simulate timing control samples.
vhdl-code-for-carwash
- automatic car wash system using verilog hdl where car moves from one state to another state for washing based on time intervel
testrom
- My Uploaded Code to test ROM using VHDL.
mux_4
- Uploaded Source code to design and implementation Multiplexcer using VHDL