资源列表
21d_ask_tz
- 数字信号形式实现模拟2ASK的调制解调功能（模拟信号抽样量化以正弦波载波形式输出）-2ASK digital signal form of analog modulation and demodulation functions (quantized analog output signal is sampled in the form of a sine wave carrier)
2FSK_tiaozhi
- 自己写的一个队2FSK模拟调制的程序（一正弦载波形式输出，抽样量化了），绝对跑得出-To write a team 2FSK analog modulation procedures (a sinusoidal carrier in the form of output, sampling quantified), definitely run out
8-bit-RISC_CPU
- 8位RISC_CPU设计的verilog源码以及工程文件、测试数据文件。在modelsim 10.1d下验证成功，打开工程文件即可使用。-8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.
ov7670
- OV7670驱动代码（源码） 只为驱动代码，输出为像素点信号，必须有相应的下层模块才能完全完成对摄像头的控制-OV7670 driver code (source) only for the driver code, the output pixel signal, there must be a corresponding lower module to fully complete camera control
I2C
- I2C控制源码 用于摄像头的信号传输和控制。 在使用时FPGA需要接上上拉电阻否则无效-I2C control source signal transmission and control for the camera. When using the pull-up resistor connected FPGA requires otherwise invalid
watch_dog
- 看门狗程序设计，使用verilog HDL语言编写-Watchdog program design, using verilog HDL language
ROCE_PCI_LED
- pci9054 上下位机通信下位机代码 -verilog project for the communication between PC and PCI board.
cpu
- 16位CPU请认真书写上传资料的详细功能、包含内容说明(至少要20个字)。尽量不要让站长把时间都花费在为您-16-bit cpu
test_led
- Verilog语言的24小时计数器，数码管显示，按键调时，在CPLD上调试正常。-Verilog language 24-hour counter, digital display, when the key tone on CPLD normal debugging.
I2C
- K2FPGA开发板实验教程——I2C协议说明及verilog实现读写I2C器件，中文内涵代码，验证可用。-K2FPGA development board test tutorial- I2C protocol descr iption and verilog read and write I2C devices, Chinese connotation code to verify availability.
ADDER_8BIT_FOR_BCD
- 基于FPGA的由两个四位全加器合成的八位全加器 -Based on the synthesis of two four eight full adder full adder FPGA
digital_clock
- 数字钟的设计，系统分为5个模块，Freq_div模块，Clock_cnt模块，Clock_ctl模块，Key_ctl模块和Display模块。系统目标：用8个LED 显示时间，如9点25分10秒显示为，09－25－10。（2）设置2个按键，按键SET用于工作模式选择，按键UP用于校时。-Digital clock design, the system is divided into five modules, Freq_div module, Clock_cnt module, Clock_ct