资源列表
encode_64_66
- 自编的64B/66B编码程序，下次上传解码程序。-the 64B/66B coding process is written by myself, i will upload the decoding process next time.
digital_voltage
- VHDL开发的数字电压表，量程5V，精度0.01V，在Sparten3E FPGA运行通过-VHDL development of digital voltmeter, range 5V, precision 0.01V, running through the Sparten3E FPGA
Frame-synchronizer-
- 原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。-Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine sync
Bit_synchronization
- 这是一个位同步的FPGA完整代码，是用Verilog写的，其中包括分频、时钟、时钟提取等各模块以及顶层文件，做调制解调的朋友可以-This is a synchronous FPGA complete code is written in Verilog, including frequency, clock, clock extraction module and the top-level file, do the modulation and demodulation of a frien
emif
- EMIF字符型设备驱动，实现了dm368与FPGA之间的通信，把FPGA当着dm368的一个ram往里面写数据和向外发数据。-The driver of EMIF .
PCI_arbi
- PCI总线仲裁参考设计Verilog代码。最大支持6个master的仲裁。-PCI bus arbitration reference design Verilog code. Maximum six master arbitration.
Sdram_Control_4Port
- SDRAM控制器的verilog源代码实现-SDRAM controller Verilog source code to achieve
dsp_core_tx_filter
- 应用在USRP N210上的XIlinx的FPGA开发板上面的变采样滤波器，实现25--30.72M的变采样滤波器，适应LTE物理层的要求-Application on the USRP N210 FPGA development board above XIlinx variable sampling filter, to achieve 25- 30.72M variable sampling filter, adapt LTE physical layer requirements
MAC_TxScheduler
- Ethernet MAC-MII interface of Transmit
SPI-Master
- 有关Verilog的SPI通信的代码,可以应用于FPGA的通信-this is verilog code about SPI
GEN_HDMI
- 基于XILINX SOC的HDMI配置的SDK工程和IP核，用于HDMI芯片的配置-XILINX SOC based on the HDMI configuration SDK engineering and IP cores for HDMI chip configuration
Parallel_SQRT
- 32-bit parallel integer square root