资源列表
clock_verilog.rar
- verilog语言实现的数字钟，各种定时闹钟功能类似真实的表~利用EDA实验平台实现~~,Verilog language implementation of the digital clock, alarm clock features a variety of regular table similar to the real experimental platform ~ using EDA implementation ~ ~
Example4
- 八位七段数码管动态显示电路设计 使用的是两个四位一体、共阴极七段数码管 学习 VHDL 的 CASE 语句及多层次设计方法-Dynamic eight seven-segment LED display circuit design uses two one four, 7-segment LED common learning CASE statement VHDL design methods and the multi-level
8b10_enc
- 8b10b解码文件，我从网上下的一个，感觉不错，传上来大家共享
sqrt_LUT8
- Square root calculation: S=N^2+d using LUT-Square root calculation: S=N^2+d using LUT
sobel
- 多级流水线8位sobel图像处理边缘检测程序-sobel edge detection
Digipot_wb_interface
- Generic Wishbone Slave interface for AD5204 driver. Instantiable in any platform.
chenxu
- 利用状态机设计正弦波信号发生器： //输出4位接4位的DA转换，即4位数字信号输出可直接通过DA转换为模拟信号。 -The use of state machine design is the sine wave signal generator:// output 4 connects a 4-bit DA converter, i.e. the 4-bit digital signal output can be directly through the DA converte
TelephoneRemoteControlSystem
- 利用电话远程系统，通过密码验证来实现对家庭电器的智能控制。-The use of long-distance telephone system, via a password to verify the implementation of the intelligent control of household electrical appliances.
Desktop
- it s a file contain Verilog code of a full adder. I hope this file is usefull for someone ! Regards !
top
- 实用的usb数据读取，实现68013数据读取，硬件实现语言-Practical usb data read, data read to achieve 68,013, the hardware implementation language
AX301_Real_time_clock_test
- AX301 FPGA开发板，实时时钟实验程序代码-AX301 FPGA development board,Real time clock test code
1TP8051
- 1T+8051单片机单串口双串口3串口测试程序.-1T+8051 chip dual-port 3 single serial port test program.