资源列表
FIRvhdl
- 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation - 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAX
CRC16
- 用于CRC16校验的Verilog程序源代码，喜欢的拿走-Uses in CRC16 the verification the Verilog procedure source code, likes taking away
NCO
- 用verilog语言写的NCO，在quartus环境中应用-Verilog language written with NCO, quartus environment in the applications
UART
- UART verlog 源码-UART verlog.......................
4945579081DCT_2D
- dct-20 verilog vhdl de2
top_module
- OFDM Gaurd Detector, Symbol length = 1024 & Gaurad Length = 256, and test bench written in verilog!
BT656_RGB
- BT656转RGB的算法实现代码，使用VORILOG语言编写-BT656-->RGB, verilog
decode_64_66
- 自编的64B/66B解码程序，做毕业设计的时候写的。-The decoding process 64B/66B , written when i am in the school。
verilog
- 一些基本器件的实现，包括选择器，计数器，移位寄存器，多位寄存器以及各种测试模块-The realization of some of the basic devices, including the selection, counters, shift registers, a number of registers and a variety of test modules
config_data
- AD的配置文件，主要针对ADI的AD转换芯片-ADI s profile, mainly for ADI AD converter chip
memoryarray
- 由VHDL撰写的两记忆体转置程序，内含testbench与转置源码。-VHDL written by the two memory migration procedures, includes testbench and migration source.
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code