资源列表
clk-div
- VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
PWM-dead-zone
- 实现PWM输出的死区控制，可保证避免上下桥臂同时导通损坏功率器件-Achieve PWM output dead time control, can guarantee to avoid simultaneous conduction of upper and lower leg damage power devices
EDA
- VHDL语言 用计数器实现分频器 N分频器-VHDL language implementation with a counter N divider divider
FIFO
- 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
counter
- 基于FPGA的计数器程序涉及，可以自由移植使用-Transplantation using FPGA-based counter program involves freedom
verilog
- Verilog的几段小代码 网上找的 仅供参考-some verilog code ,only for reference
lcd5110
- Nokia 5110 液晶的显示控制，SPI接口实践，基于vhdl开发-Nokia 5110 LCD Display Control, SPI interface practices, developed based on vhdl
ssram_latest.tar
- SSRAM接口,就是同步静态随机存取存储器接口整个工程文件，包括从前端verilog设计到后端仿真的整个工程-SSRAM interface is synchronous static random access memory interface entire project, including the design from the front to the back verilog simulation of the entire project
timer.tar
- this a 32-bit general purpose timer.-one time mode continue mode
CRC_module_of_FPGA
- 利用VHDL语言编写的一个crc功能模块，可下载到FPGA实现功能-use VHDL to prepare a crc function of the module, which can be downloaded to the FPGA functions
10BASET_RxD
- this is 10 base rxd application
uart-to-GPIO.vhd
- -- Filename ﹕ uart.vhd -- Author ﹕ZRtech -- Descr iption ﹕串口接收与发送程序 -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证-- 程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位-- 8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波-- 特率。程序当前设定的div_