资源列表
cpldsvfs
- VHDL Interfaces and Example Designs
RD1088_rev01.2
- FPGA或CPLD读取SD卡的IP核，基于wishbone接口，支持SDHC2.0，包含了使用说明，为Verilog语言编写-FPGA or CPLD reads the SD card IP core, based on the wishbone interface, support SDHC2.0, contains instructions for the Verilog language
DS18B20
- Quartus 9.0 ，VHDL语言写的ds18b20 温度测量，1602液晶显示，还有报警功能，开发板用的是EP1C12F3234C8。-Quartus 9, VHDL language to write the DS18B20temperature measurement,1602 liquid crystal display, and the alarm function, development board is used in EP1C12F3234C8
s17_flash
- VHDL 如何操作flash,源代码很详细的哦-VHDL for flash
Sandeepani-VERILOG-material
- sandeepani institute verilog material
Xilinx_FPGA_FFT_应用笔记
- Xilinx公司的FPGA_FFT_应用笔记，详细通俗的讲解了fft算法(Xilinx's FPGA_FFT_ application notes, in detail, explain the FFT algorithm.)
liushuideng
- 基于Verilog HDL的流水灯例程，在quartus 11.0上结合DE0运行-Verilog HDL-based flow lamp routine
ltc1196.rar
- TLC1196串行AD控制模块，可以实现对电压的信号采集，并以串行的方式传送到FPGA中,TLC1196 Serial AD control module can be achieved on the voltage of the signal acquisition, and serial transmission of the FPGA
miaobiao
- 计数秒表，实现23进制计数清零，同时可以更改分频-Counting stopwatch, to achieve 23 decimal count is cleared and you can change the frequency
fpga-fir
- 使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog langua
de2_build
- De2_build: It contains the FPGA configuration file of the comprehensive Nios II system in Section 16.10.2 and software image files for the DE2 board. These files can be used for quick demo or software development. Note that the files can only be us
VerilogHDL_DC_Motor_control
- verilog实际开发例子，非常适合初学者学习-verilog examples of actual development, ideal for beginners to learn