资源列表
motor
- 常见的几种电机的特征与控制方法
Verilog_gopi
- it is an excellent ppt to learn verilog hdl by your own
lab6
- de2 altera 实验7 finite state machines 答案-de2 altera experiment 7 finite state machines answer
zyclock
- 采用EDA技术，使用Quartus实现了数字秒表的设计，能跑通-Using EDA technology, the use of Quartus achieve a digital stopwatch, run through
Reading-User-Data-from-Proms
- FPGA的配置中，从Flash中读写用户数据，包括VHDL、Verilog程序-in configuring FPGA,reading and writing user data from flash,including the VHDL and Verilog code
FPGA-频率计（等精度测频+SPI通信）
- 本程序采用FPGA编程，实现等精度测频的程序，并且有实现SPI通信的程序。(This procedure uses FPGA programming, such as precision frequency measurement procedures, and to achieve SPI communication procedures.)
FPGA6_LCDaUART
- 基于FPGA Verilog LCD显示串口数据-Based on the FPGA Verilog LCD display serial data
EDA
- 通过MAXPLUS软件做时钟信号发生器，可通过外部的拨码开关进行清零和预置数-Software made by MAXPLUS clock signal generator is available through an external DIP switch and preset number of cleared
music_player
- 音乐播放器，各模块使用VHDL写的，拥有暂停功能。jishu模块根据时钟信号产生八位递增的地址信号，传到music模块。music模块存放音乐的数据，根据得到的地址输出音阶。tonetab接收到音阶信号后会输出当前的音阶是多少，是否为高八度，用于数码管显示，同时将此音阶需要的分频率传给speaker模块。speaker模块根据接受到的分频比对2M的时钟进行分频，然后送给蜂鸣器发出声音。-Music player, each module written in VHDL, with pause f
CPU
- 东南大学COA下实验设计CPU完整程序，可以在RAM中写程序并可观察各个输出的波形，用于检验。-south-east university COA II the design cpu lesson which you can write your own program in the cpu and also can chack the wave
Verilog-HDL
- VerilogHDL实践与应用系统设计随书代码-VerilogHDL practice and application of system design with the code book
SOPC_picture
- 基于sopc的数码相框设计，有具体的代码，操作步骤-Digital photo frame design based on sopc code specific steps