资源列表
scramble
- 在quartusII上已经验证过，很有用的并行加扰程序，用的语言为verilog，需要的可以拿去-Has already been verified in quartusII useful parallel scrambling procedure, the language used for Verilog, need to take look at
ASIC_and_FPGA_Verification
- ASIC/FPGA验证经典资料，英文版，希望大家可以有所借鉴。-ASIC/FPGA verification classic information, in English, I hope that we can learn from there.
VHDL
- 内容1：哈尔滨工程大学信息与通信工程学院的课件-适合初学VHDL语言的人。内容2：VHDL语言详解的讲义。-1: Harbin Engineering University College of Information and Communication Engineering of software- suitable for novice VHDL language. Content 2: VHDL language of the notes explain.
verilog-procedures
- fpga的基于verilog的串行数据转并行数据的相关资料，相关内容uart协议，串并转换程序-verilog fpga-based serial data to parallel data, relevant information, relevant content uart protocol string and conversion program
soure
- 用VHDL开发NES程序。这里是其配套的详细的VHDL语言源码。可用quartus进行验证。-NES with the VHDL development process. Here is the complete source of detailed VHDL language. Quartus available for verification.
12-ATK-NEO-6M-GPS
- 用keil打开，编译后导入STM32 GPS模块与STM32的协同工作，可以接收并解码GPS的信号。-Use keil to open, compile and import STM32 The GPS module works with STM32 to receive and decode GPS signals.
ASICandFPGAVerificationAGuideToComponentModeling.
- ASIC AND FPGA VERIFICATION: A GUIDE TO COMPONENT MODELING by RICHARD MUNDEN
Ch
- design of cache to remove tag bits
ASIC-and-FPGA-Verification---A-Guide-To-Component
- ASIC and FPGA Verification - A Guide To Component Modeling
exp3.2_key4x4
- key4*4 键盘扫描FPFA代码 实现按键功能-key4* 4 keyboard scan code key functions FPFA
Buzzer
- 基于FPGA EP3C16芯片的Buzzer程序，使用Verilog语言编写，已测试通过，引脚已分配好-FPGA EP3C16 chip Buzzer-based program, use the Verilog language, have been tested, the pin has been assigned
ASIC-and-FPGA-Verification---A-Guide-To-Component
- ASIC and FPGA Verification - A Guide To Component Modeling