资源列表
clock
- vhdl 简易数字钟 基于fpga 使用quartus7.0，便于移植到其他平台
IEEE_Standard_verilog_std_1364_1995
- Here is verilog standard which u may find useful! share share
DSO_Project
- 数字示波器FPGA程序, 魏昆申第二版。-digital oscilloscope fpga source
DDS
- 基于IP核设计的波形发生器以及频率计并用数码管显示-With digital display IP core design based waveform generator and frequency counter
New
- VHDL Learning book Very Good
Tetris-game-based-on-FPGA
- 在FPGA开发板上实现俄罗斯方块游戏的功能，可以链接电脑显示器并使用电脑键盘来控制。-A Tetris game based on FPGA
trafic
- trafiic controller with test bench
bram_delay
- Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
1.UART
- uart通信的verilog历程，已经过测试-uart communication
pli1
- Pli verilog编程接口说明书，使用此说明书既可以学习如何调用使用Pli接口对程序进行编程。-Pli User’s guide
OQAM_PREPRO
- OQAM modulation VHDL code
fir
- 真正意思上的fir滤波器课程设计，基于quartus II9.0的vhdl代码。有原理图输入和例化元件-The real meaning of the fir filter design program, based on quartus II9.0 the vhdl code. A schematic of components and cases