资源列表
AX301_jtag_uart_test
- 黑金AX301开发板，jtag口驱动及调试实验代码-AX301 development board,JTAG port driver and debug experiment code
digital_clock
- 基于vivado的FPGA数字闹钟的程序，verilog语言编写-Vivado based on the FPGA digital alarm clock procedures, verilog language
timer
- Simple 32-bit timer realization with APB interface with support of interrupt generation and switching clock source.
Vhdl-code-a-testbench
- 基于VHDL编写的LED灯程序及testbench-LED code & testbench for VHDL
RAM2048X8
- you can add this code to your project if you need RAM2048X8
hp and lp filter
- hp and lp filter verilog code..
FIFO_RAM
- 同步FIFO_RAM的设计及其testbench(8 bit SYN FIFO module fifo_v(clk,rst,wen,ren,full,empty,data,q);)
i2c_master
- verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
code.sources
- 秒表代码加上相应的key，测试通过可以直接用于vivado(zcscscsasfsdfsfasfasf)
sin
- 能够实现正弦波的输出以及通过频率控制字与相位控制字控制正弦波的相位与频率。(The output of the sine wave can be realized and the phase and frequency of the sine wave can be controlled by two control words.)
cordic
- 使用verlog语音实现cordic 算法，在DE2 115平台上已验证。(Implementation cordic algorithm)
HEX2BCD
- 十六进制转BCD,包含设计文件和仿真文件，工程文件(Sixteen decimal to BCD, including design documents and simulation files, engineering documents)