资源列表
project.map
- D Flip Flop for Single Bit Store
DDS的VERILOG原代码
- 实现了DDS的verilog源代码，可以使用(ajhsjdhjkshfjhfsjkjksa)
i2c_slave
- iic slave端，项目中已经用过，可用适用所有传输速率，板间通信，接口少的情况下，可用该程序实现多参数传输，状态监控。(The IIC slave terminal has been used in the project. It can be applied to all kinds of transmission rate, inter board communication and less interfaces. The program can achieve multi param
New folder
- verilog codes for counter,d flipflop,fibonacci series,prime numbers,top.
digital_clock
- 自己用verilog HDL写的一个数字钟模块，包括校时功能，在Maxplusii下调试和下载通过(A digital clock module written by Verilog HDL, including timing function, debugging and downloading through Maxplusii.)
lab2
- 基于FPGA的智力抢答器，基于Xilinx器件，包含主程序、仿真代码。(Intelligent answering machine based on FPGA)
fifo
- fifo模块，改模块使用同步fifo设计，里面包含一些设计技巧，读延迟最少(The module of FIFO is modified by using synchronous FIFO, which contains some design skills and the least latency.)
Desktop
- 一个简单的8 - 3 编码器，主要适用于初学人员参考，很好的例程。(A simple program means to encoder.)
ddc
- 下变频采样、本振和滤波三个过程涉及到的详细代码与注释(Detailed code and notes for down conversion sampling, local oscillator and filtering)
sram_sp_hse_8kx8
- SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8 Chip memory Chip memory)
elevator
- 八层电梯，有密码开关，警报开关，quartusⅡ综合，cycloneⅤ的板子(There are password switches, alarm switches, and eight layers of elevator display, Quartus II synthesis, cyclone V board.)
POC
- 实现了计算机系统中作为I/O模块的POC。(It simulates the POC module which works as an I/O module in a computer system.)