资源列表
UP3_RTC_CLOCK
- 在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒，具有闹钟，整点报时，时间可重新设置等功能，在LCD1602上显示。绝对推荐，比网上其他类似代码功能要全而且经过验证。最关键的是该代码是直接通过I2C总线来获取UP3开发板上的实时时钟芯片的时间的,当然也可以通过I2C对时钟芯片进行设置.
shiyan
- OFDM中的信道均衡技术对于研究如何消除噪声干扰以及去除相位偏移的有着重要的作用-OFDM channel equalization techniques in the study of how to eliminate noise and to remove the phase offset has an important role in
gensin
- 用fpga控制da发一定带宽正弦信号，用vhdl编写，用nco-Fpga controlled by a band-da made a sinusoidal signal, written in vhdl, with nco
01
- 特权同学的SDRAM代码及详解，非常有用。-Privileged students SDRAM code and detailed, very useful.
Simple_Logic_Continue
- quartusII 9编写的74161模块，简单的例子，可以直接运行-The module 74161 with the language of verilog
hw5
- Design a 2-digit stopwatch that ticks every second. A switch is used to start and stop the time. When the switch is pushed, the time will start and when it is pushed again, the time will stop. In order for the switch to work properly, the switch must
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
DDS
- 这个是我自己用VHDL语言写的两相数字信号发生器程序 D/A用的是DAC904-This is for my own use VHDL, written procedures for two-phase digital signal generator D/A using a DAC904
LED-dynamic-testing
- eda实验资料，led灯动态扫描实验，有完整的图及程序-eda experimental data led lights dynamic scanning experiments, complete plans and procedures
ISE-Development-of-advanced
- Xilinx公司ISE开发环境的开发进阶，对于更高层次的FPGA开发者有很好的帮助。-Xilinx s ISE development environment, the development of advanced, have a good help for the higher-level FPGA developers.
8bitDDS
- 用于产生8bit 的DDs 信号发生器的代码-code of dds
DE2_USB_API
- 这个是DE2实验板上关于USB控制的全部资料，具体请大家细看-This is experimental DE2 board all the information on the USB Control, specifically Please take a closer look