资源列表
DE2_system_USB_API
- DE2_system_USB_API ALTERA的DE2开发板卡的资料-DE2_system_USB_API ALTERA DE2 board
Verilog
- ：Verilog实现的DDS正弦信号发生器和测频测相模块-: Verilog implementation of the DDS sine signal generator and frequency measurement module test phase
LCD1602
- 基于altera cyclone 的EP2Q208C8 FPGA的1602液晶显示模块，其中包括驱动模块和测试模块，驱动模块可以作为通用模块，给其他文件调用-Altera cyclone display module is based on the 1602 LCD EP2Q208C8 FPGA, including drive module and test module, drive module can be used as general-purpose modules to other
Design-Recipes-for-FPGAs
- that the fpga design for digital circuit and new technology design
ser_to_parr
- 很有用的10bit串并转换verilog程序，需要的可以拿去参考下，在quartusII上已验证过-Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII
Newnes_Design_Recipes_for_FPGAs
- This book is designed to be a desktop reference for engineers, students and researchers who use Field Programmable Gate Arrays(FPGA) as their hardware platform of choice.
chap2
- VHDL的CPU仿真与实现 很好的源代码介绍-The CPU simulation and VHDL source code to achieve a good descr iption
关于DDS的相位变化的VHDL程序
- 关于DDS的相位变化的VHDL程序
Altera-Cyclone-III
- Altera Cyclone III Component library
Digital_Clock_VHDL
- 使用VHDL开发的简易数字时钟软件，可以作为初学者熟悉定时器应用的实例程序。-Use VHDL to develop a simple digital clock software can be used as timers for beginners familiar with examples of the application process.
crc_8
- 基于verilog的并行crc8的校验，已经仿真过，符合设计要求，可以拿去参考-Verilog a parallel crc8 checksum, already simulation, meet the design requirements, you can take reference
ds18b20
- 基于FPGA的VERILOG语言的DS18B20温度检测程序，很好用-FPGA-based VERILOG language DS18B20 temperature testing procedures, very good use