资源列表
I2CVerilog
- VerilogHDL 实现了I2C 文件中包含六个程序 第一个为主程序 其余为子程序 -VerilogHDL achievement of the I2C document contains procedures for the first six the rest of the main program for the subroutine
vhdl
- 基于FPGA的实现一个电子时钟的VHDL语言-digital clock design with VHDL
div16
- 十六位的除法器，采用verilog hdl-16 of the divider using verilog hdl
delay-12
- 延时N个脉冲时间，在这里是延12个脉冲，4个通道。-delay 12
fir128
- Discrete-Time FIR Filter, Filter length - 128, Number of Multipliers - 8, Number of States - 8.
74-Hamming-code-encoder-and-decoder
- 基于VHDL实现（7，4）汉明码的编码器和译码器-VHDL-based implementation (7,4) Hamming code encoder and decoder
THE-FIR-Base-on-FPGA
- 基于fpga的FIR滤波器实现，程序为11阶滤波器实现的源代码-Fpga-based FIR filter implementation, the source code
multiplier
- 利用Wallace乘法器树原理写的乘法器，6：2的基本单元-Multiplier using Wallace tree multiplier principle of writing, the basic unit of 6:2
STC-GY-27-ADXL345-IIC
- STC-GY-27-ADXL345 IIC测试程序 // GY-29 ADXL345 IIC测试程序 // 使用单片机STC89C51 // 晶振：11.0592M // 显示：LCD1602 // 编译环境 Keil uVision2-STC-GY-27-ADXL345 IIC test program// GY-29 the ADXL345 the IIC test program// use microcontroller STC89C51// crystal: 11
kb
- 基于niosII系统的PS2键盘测试程序，测试PS2键盘与niosII内核的通信是否成功。该程序在Quartus自带的eclipes下编译运行。-Based nios II system PS2 keyboard test procedures, test PS2 keyboard and niosII kernel communication is successful. Compile and run under Quartus comes eclipes.
Example3
- 含异步清零和同步使能的加法计数器 二进制计数器是应用最多、功能最全的计数器之一，含异步清零和同步使能 的加法计数器的具体工作过程-Including synchronous and asynchronous clear to enable the addition counter binary counter is the most widely used one of the most versatile counter with asynchronous clear and spec
xor
- 异或门的FPGA实现的verilog代码-xor FPGA realization of the verilog code