资源列表
NIOS PWM HAL
- NIOS环境PWM的USER LOGIC实例4-NIOS environment PWM USER LOGIC example 4
decode12
- codes for different modules in verilog
SourceCode
- 生成非标视频行场同步信号及锯齿波驱动电机(Generating non-standard video line field synchronous signal and sawtooth wave drive motor)
I2C
- i2c core : top module
LED_clock_quartus
- 用VHDL语言实现数显时钟，devid200.vhd为分频模块，scan.vhd为LED扫描模块，timecount.vhd为计数模块-VHDL digital clock, devid200.vhd for frequency module, scan.vhd for LED scanning module, timecount.vhd for counting module
4multiplier
- 4位乘法器vhdl程序-- DEscr iptION : Signed mulitplier:-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 7-4 multiplier vhdl procedure
iic_sfp
- IIC SFP接口测试程序，Xilinx参考设计，ML507硬件测试通过-IIC SFP interface test code，Xilinx reference design，tested on ML507 platform.
cpu16
- 一个16位cpu的vhdl代码。具体内容我也不清楚，自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
PNSequence
- pseudo noise generation
NIOS_UART
- FPGA QUARTUS 异步串行口通讯模块程序，常用模块。-FPGA QUARTUS sync serial communication routine,uart.
vhdl
- VHDL的论文，有关出租车计费器的设计，很好。-VHDL
FPQ
- 基于FPGA的数控分频器，可以吧一个时钟信号分成不同频率的时钟信号。-FPGA-based digital frequency divider, a clock signal can now be divided into different frequency clock signals.