资源列表
LIBRARY-IEEE
- 8位数码管的动态显示（包括对数码管的位选以及段选）-8 digital control dynamic display
UART
- verolog语言编写，功能如标题所示。有问题请联系mxkmxm@126.com-verolog language, functions such as the title indicates. There are problems, please contact mxkmxm@126.com
qiangdaqi
- 描述的是一个8位的抢答器，相信对初学者有所帮助-Described is a 8 bit responder, believe to be helpful for beginners
ARM9_instruction_cache_verilogCodes
- Arm9指令Cache缓存模块的verilog代码，对一些做ARM硬件开发的朋友有参考价值。-Arm9 Instruction Cache Cache Module Verilog code, do some of the hardware development of the ARM friends reference value.
weimafashengqi-achieved-by-verilog
- 该代码用Verilog语言实现了M序列的伪码产生，伪码特征方程为X13 +X7+X5+1，已通过仿真验证。-The code in Verilog realize the M-sequence pseudo-code generation, pseudo-code characteristic equation for the X13+ X7+ X5+ 1, it has been verified by simulation.
dlx_modules.v
- 经典dlx module文件，if和id模块做了部分修改-Classic dlx module file, if id module and made some modifications
eclock
- MAXPULS II 下VHDL实现多功能电子钟的源代码，包括时钟，秒表，日历等多种功能-MAXPULS II under VHDL multifunctional electronic clock source code, including the clock, stopwatch, multiple functions such as calendar
-TLC5510-VHDL
- 学习控制的好资料，可以很快掌握学习方法，慢慢研究会有收获的-Learning control of good information, you can quickly learn to master the method of study will be harvested slowly
fft128
- This 128 point fft code in verilog-This is 128 point fft code in verilog
TLC5510-VHDL-controller
- TLC5510的控制与仿真源代码，是初学者的良好参考-TLC5510 control and simulation source code, is a good reference for beginners
CHUANKOU
- 通过对时钟分频，串口接收和发送以及串口调试程序的编写实现数据的接受和发送-Through the clock divider, and a serial port receive and transmit serial debugging procedures for the preparation of the receiving and sending data
crc16
- verilog 语言下的硬件CRC校验：CRC16(CRC verification in Verilog: CRC 16)