资源列表
STARTER_VGA
- SPARTAN3E500 GVA VERILOG语言-SPARTAN3E500 GVA
Timer
- 基于verilog xilinx spartan 3e100的秒表计时器-Based verilog xilinx spartan 3e100 stopwatch timer
segment
- 基于verilog xilinx spartan 的7段管显示-7-segment tube display based on verilog xilinx spartan
run
- verilog HDL PARTAN 3E100的流水灯程序-verilog HDL PARTAN 3E100 water light program
arb
- verilog round robin arbiter
cntrlr
- verilog code for bus controller
atm_cell
- verilog code for atm_ce-verilog code for atm_cell
alarm
- vhdl alarm design code-vhdl alarm design code
syncram
- verilog rtl and testbench code for single port sync ram
project
- VHDL编写的ATM代码,能实现全部的功能，经过了测试和仿真。-VHDL code written in ATM, can realize all the functions, after the test and simulation.
bahe
- 采用verilog设计的拔河比赛，在QuartusII9。0仿真验证并在DE2上测试过-Using Verilog to design the tug of war, in QuartusII9. 0 simulation and test on DE2
20_lcd
- 一种基于verilog和quartusII的液晶显示驱动的封装，LCD（12864）封装。-Verilog and quartusII based LCD display driver package, LCD (12864) package.