资源列表
UniversalRegister
- 这种设计是一个普遍的登记册可作为一个简单的存储登记，双向移位寄存器，计数器的行动和反跌。登记册可以载入了一套并行数据输入和模式是由3位输入。-This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. The register can be
adc16
- 此例程是针对FPGA的16位模拟数字转换器的程序，相信这对需要进行模数转换的朋友辉用到的-This routine is for the FPGA of 16-bit analog-to-digital converter program, I believe this is the need for analog-to-digital converters used in a friend-hui
VHDL_DS18B20
- DS18B20的VHDL语言控制方式。D S18B20的VHDL语言控制方式。-DS18B20 control of the VHDL language. DS18B20 control of the VHDL language. DS18B20 control of the VHDL language.
Prashanth_Chandran_thesis
- thesis based on symbol timing recovery based on fpga
modelsim
- 教程学习MODELSIM,江西介绍了怎么运用改仿真软件进行各种仿真和优化设计-A detailed information of MODELSIM
dianfengshan
- 能实现智能风扇控制,包括模式选择.摇头.定时等功能.-To achieve the smart fan control, including the mode selection. Shook his head. Timing functions.
taxi
- 用vhdl语言编写,能实现功能强大的出租车计价功能.-Vhdl language used, to achieve Taximeter powerful features.
boxingcunchuqi
- 功能强大的波形存储器,对输入的波形进行存储.-Powerful waveform memory, the waveform of the input store.
Reuse-Methodology-Manual-Third-Edition
- 进行SOC/IP 设计以及可重用设计的宝典书籍！是synopsys的一位牛牛写的！ 主要以mentor和synopssy的设计工具为流程，讲述了SOC/IP可重用设计，验证设计的基本方法。 -For SOC/IP design and reusable design book books! A synopsys Niuniu is written! To mentor and synopssy the main design tools for the process, about the
quartus-work
- 基于FPGA的VERILOG的分频器的设计，10分频设计的源代码和设计思路-Based od FPGA
vhdl1602
- vhdl和ixiande1602初始化该代码精简！通俗易懂！是初学者的天堂！-vhdl 1602
lab1
- system generator/simulink 应用开发实例，User Starting