资源列表
VHDLerror
- 介绍了在使用FPGA进行设计时，出现的VHDL编程错误-Introduced to the use of FPGA design, VHDL programming error occurred
vhdl
- VHDL设计的实例，用实例讲述VHDL的编程方法-VHDL design examples, using examples of programming method on the VHDL
s2p
- 一个很好的串并转换verilog代码，带有modelsim仿真文件-very good
ead
- VHDL设计初步，一些基本的程序。希望大家支持学习。-VHDL design of a preliminary, some basic procedures. I hope you will support learning.
veval
- It is vhdl code for defining a finite state machine
FSM_Mealy
- 借助该MEAL状态机源码您就可以轻松设计自己需要的状态机-MEAL state machine with the source code you can easily design their own state machine needs
HELLO
- 等精度频率计1hz-50khz,门控型号影响大,由p2.7脚嬴出-frequency
fpga
- 用Verilog语言实现USB2.0的串口通信-Verilog
dds_first
- 用vhdl语言，通过加法器和寄存器实现fpga的dds功能-Using vhdl language, and register through the adder to achieve the fpga functional dds
IICVHDL
- IIC，给予VHDL的IIC的实现，很好的资料-NO