资源列表
myprogram
- hi view it its my first code in vhdl
Morgan.Kaufmann.VHDL.2008.Just.the.New.Stuff.Dec.
- A tutorial e-book fo VHDL by Kaufma-A tutorial e-book fo VHDL by Kaufmann
FPGADDS
- dds，FPGA波形发生器,波表，接受，发送-dds, FPGA waveform generator, wave form, to receive, send
WaveletCompression
- wavelet compression describes the compression techniques
s7enable_send0x55_UART_9600
- 最简单的UART发送程序，vhdl编写，系统时钟40M，波特率9600，外Load有效（一个高脉冲）即向PC发送一个字节0X-UART to send the simplest procedures, vhdl prepared, the system clock 40M, baud rate 9600, outside the Load effective (a high-pulse) to the PC sends a byte 0X55
steppermotordrive_latest.tar
- stepper motor control through vhdl coding
1111111
- 16位定点FFT-DSP的FPGA实现-16-bit fixed-point FFT-DSP for FPGA realization
1231234
- FFT在fpga下实现-FFT in fpga to achieve! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
fenpinji
- 设计了一种分频器，能够将所给的频率分成较小的频率。可以适当修改其中的参数，使频率达到设计者要求-The design of a prescaler, which can be divided into smaller frequency to frequency. Appropriate changes to the parameters, so that the frequency of the designer to achieve the requirements
half_adder
- 一个半加器，具有进位和位数相加的基本功能，可作为全加器的基本模块-One and a half adder with binary and the sum of the basic functions of the median, full adder can be used as the basic module
LCD1
- lcd controller using vhdl code